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an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. production data. sn74lvc2g74 sces203p ? april 1999 ? revised july 2016 sn74lvc2g74 single positive-edge-triggered d-type flip-flop with clear and preset 1 1 features 1 ? available in the texas instruments nanofree ? package ? supports 5-v v cc operation ? inputs accept voltages to 5.5 v ? max t pd of 5.9 ns at 3.3 v ? low power consumption, 10- a max i cc ? 24-ma output drive at 3.3 v ? typical v olp (output ground bounce) < 0.8 v at v cc = 3.3 v, t a = 25 c ? typical v ohv (output v oh undershoot) > 2 v at v cc = 3.3 v, t a = 25 c ? i off supports live insertion, partial-power-down mode, and back-drive protection ? latch-up performance exceeds 100 ma per jesd 78, class ii ? esd protection exceeds jesd 22 ? 2000-v human-body model ? 200-v machine model ? 1000-v charged-device model 2 applications ? servers ? led displays ? network switch ? telecom infrastructure ? motor drivers ? i/o expanders 3 description this single positive-edge-triggered d-type flip-flop is designed for 1.65-v to 5.5-v v cc operation. nanofree ? package technology is a major breakthrough in ic packaging concepts, using the die as the package. a low level at the preset ( pre) or clear ( clr) input sets or resets the outputs, regardless of the levels of the other inputs. when pre and clr are inactive (high), data at the data (d) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. following the hold-time interval, data at the d input can be changed without affecting the levels at the outputs. this device is fully specified for partial-power-down applications using i off . the i off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. device information (1) part number package body size sn74lvc2g74 sm8 (8) 2.95 mm 2.80 mm vssop (8) 2.30 mm 2.00 mm dsbga (8) 1.91 mm 0.91 mm (1) for all available packages, see the orderable addendum at the end of the data sheet. simplified schematic productfolder d q q clr pre clk support &community tools & software technical documents sample &buy
2 sn74lvc2g74 sces203p ? april 1999 ? revised july 2016 www.ti.com product folder links: sn74lvc2g74 submit documentation feedback copyright ? 1999 ? 2016, texas instruments incorporated table of contents 1 features .................................................................. 1 2 applications ........................................................... 1 3 description ............................................................. 1 4 revision history ..................................................... 2 5 pin configuration and functions ......................... 3 6 specifications ......................................................... 4 6.1 absolute maximum ratings ...................................... 4 6.2 esd ratings .............................................................. 4 6.3 recommended operating conditions ....................... 5 6.4 thermal information .................................................. 5 6.5 electrical characteristics ........................................... 6 6.6 timing requirements, ? 40 c to +85 c ..................... 6 6.7 timing requirements, ? 40 c to +125 c ................... 6 6.8 switching characteristics, ? 40 c to +85 c ............... 7 6.9 switching characteristics, ? 40 c to +125 c ............. 7 6.10 operating characteristics ........................................ 7 6.11 typical characteristics ............................................ 7 7 parameter measurement information .................. 8 8 detailed description .............................................. 9 8.1 overview ................................................................... 9 8.2 functional block diagram ......................................... 9 8.3 feature description ................................................... 9 8.4 device functional modes .......................................... 9 9 application and implementation ........................ 10 9.1 application information .......................................... 10 9.2 typical power button circuit .................................. 10 10 power supply recommendations ..................... 11 11 layout ................................................................... 12 11.1 layout guidelines ................................................. 12 11.2 layout example .................................................... 12 12 device and documentation support ................. 13 12.1 receiving notification of documentation updates 13 12.2 community resources .......................................... 13 12.3 trademarks ........................................................... 13 12.4 electrostatic discharge caution ............................ 13 12.5 glossary ................................................................ 13 13 mechanical, packaging, and orderable information ........................................................... 13 4 revision history note: page numbers for previous revisions may differ from page numbers in the current version. changes from revision o (january 2015) to revision p page ? changed ssop to sm8 in device information table .............................................................................................................. 1 ? updated pinout images to new format .................................................................................................................................... 3 ? added pin number for dsbga package in pin functions table ............................................................................................. 3 ? changed 6 pins to 8 pins in thermal information table ...................................................................................................... 5 ? changed 23 to 2.3 for t su data in timing requirements, ? 40 c to +125 c ........................................................................... 6 ? added receiving notification of documentation updates section and community resources section .............................. 13 changes from revision n (july 2013) to revision o page ? added applications , device information table, pin functions table, esd ratings table, thermal information table, typical characteristics , feature description section, device functional modes , application and implementation section, power supply recommendations section, layout section, device and documentation support section, and mechanical, packaging, and orderable information section. ................................................................................................. 1 changes from revision m (february 2007) to revision n page ? changed i off description in features . ...................................................................................................................................... 1 ? added parameter values for ? 40 to +125 c temperature ratings in electrical characteristics table. .................................... 6 ? changed timing requirements, ? 40 c to +85 c table. ......................................................................................................... 6 ? added timing requirements, ? 40 c to +125 c table. ........................................................................................................... 6 ? changed switching characteristics, ? 40 c to +85 c table. ................................................................................................... 7 ? added switching characteristics, ? 40 c to +125 c table. ..................................................................................................... 7
3 sn74lvc2g74 www.ti.com sces203p ? april 1999 ? revised july 2016 product folder links: sn74lvc2g74 submit documentation feedback copyright ? 1999 ? 2016, texas instruments incorporated 5 pin configuration and functions dct package 8-pin sm8 top view dcu package 8-pin vssop top view yzp package 8-pin dsbga bottom view see mecahnical drawings for dimensions. pin functions pin type description name vssop, sm8 dsbga clk 1 a1 i clock input clr 6 c2 i clear input - pull low to set q output low d 2 b1 i input gnd 4 d1 ? ground q 5 d2 o output q 3 c1 o inverted output pre 7 b2 i preset input - pull low to set q output high v cc 8 a2 ? supply 1 clk 8 v cc 2 d 7 pre 3 q 6 clr 4 gnd 5 q not to scale 1 2 d c b a not to scale gnd q q clr d pre clk v cc
4 sn74lvc2g74 sces203p ? april 1999 ? revised july 2016 www.ti.com product folder links: sn74lvc2g74 submit documentation feedback copyright ? 1999 ? 2016, texas instruments incorporated (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) the input negative-voltage and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. (3) the value of v cc is provided in the recommended operating conditions table. 6 specifications 6.1 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) (1) min max unit v cc supply voltage ? 0.5 6.5 v v i input voltage (2) ? 0.5 6.5 v v o voltage range applied to any output in the high-impedance or power-off state (2) ? 0.5 6.5 v v o voltage range applied to any output in the high or low state (2) (3) ? 0.5 v cc + 0.5 v i ik input clamp current v i < 0 ? 50 ma i ok output clamp current v o < 0 ? 50 ma i o continuous output current 50 ma continuous current through v cc or gnd 100 ma t stg storage temperature ? 65 150 c (1) jedec document jep155 states that 500-v hbm allows safe manufacturing with a standard esd control process. (2) jedec document jep157 states that 250-v cdm allows safe manufacturing with a standard esd control process. 6.2 esd ratings parameter definition value unit v (esd) electrostatic discharge human body model (hbm), per ansi/esda/jedec js-001, all pins (1) 2000 v charged device model (cdm), per jedec specification jesd22-c101, all pins (2) 1000
5 sn74lvc2g74 www.ti.com sces203p ? april 1999 ? revised july 2016 product folder links: sn74lvc2g74 submit documentation feedback copyright ? 1999 ? 2016, texas instruments incorporated (1) all unused inputs of the device must be held at v cc or gnd to ensure proper device operation. see implications of slow or floating cmos inputs , scba004 . 6.3 recommended operating conditions over operating free-air temperature range (unless otherwise noted) (1) min max unit v cc supply voltage operating 1.65 5.5 v data retention only 1.5 v ih high-level input voltage v cc = 1.65 v to 1.95 v 0.65 v cc v v cc = 2.3 v to 2.7 v 1.7 v cc = 3 v to 3.6 v 2 v cc = 4.5 v to 5.5 v 0.7 v cc v il low-level input voltage v cc = 1.65 v to 1.95 v 0.35 v cc v v cc = 2.3 v to 2.7 v 0.7 v cc = 3 v to 3.6 v 0.8 v cc = 4.5 v to 5.5 v 0.3 v cc v i input voltage 0 5.5 v v o output voltage 0 v cc v i oh high-level output current v cc = 1.65 v ? 4 ma v cc = 2.3 v ? 8 v cc = 3 v ? 16 ? 24 v cc = 4.5 v ? 32 i ol low-level output current v cc = 1.65 v 4 ma v cc = 2.3 v 8 v cc = 3 v 16 24 v cc = 4.5 v 32 t/ v input transition rise or fall rate v cc = 1.8 v 0.15 v, 2.5 v 0.2 v 20 ns/v v cc = 3.3 v 0.3 v 10 v cc = 5 v 0.5 v 5 t a operating free-air temperature ? 40 125 c (1) for more information about traditional and new thermal metrics, see the semiconductor and ic package thermal metrics application report. (2) the package thermal impedance is calculated in accordance with jesd 51-7. 6.4 thermal information thermal metric (1) sn74lvc2g74 unit dct dcu yzp 8 pins r ja junction-to-ambient thermal resistance (2) 220 227 102 c/w
6 sn74lvc2g74 sces203p ? april 1999 ? revised july 2016 www.ti.com product folder links: sn74lvc2g74 submit documentation feedback copyright ? 1999 ? 2016, texas instruments incorporated (1) all typical values are at v cc = 3.3 v, t a = 25 c. 6.5 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) parameter test conditions v cc ? 40 c to +85 c ? 40 c to +125 c unit recommended min typ (1) max min typ max v oh i oh = ? 100 a 1.65 v to 5.5 v v cc ? 0.1 v cc ? 0.1 v i oh = ? 4 ma 1.65 v 1.2 1.2 i oh = ? 8 ma 2.3 v 1.9 1.85 i oh = ? 16 ma 3 v 2.4 2.4 i oh = ? 24 ma 2.3 2.3 i oh = ? 32 ma 4.5 v 3.8 3.8 v ol i ol = 100 a 1.65 v to 5.5 v 0.1 0.1 v i ol = 4 ma 1.65 v 0.45 0.45 i ol = 8 ma 2.3 v 0.3 0.3 i ol = 16 ma 3 v 0.4 0.4 i ol = 24 ma 0.55 0.55 i ol = 32 ma 4.5 v 0.55 0.55 i i data or control inputs v i = 5.5 v or gnd 0 to 5.5 v 5 5 a i off v i or v o = 5.5 v 0 10 10 a i cc v i = 5.5 v or gnd, i o = 0 1.65 v to 5.5 v 10 10 a i cc one input at v cc ? 0.6 v, other inputs at v cc or gnd 3 v to 5.5 v 500 500 a c i v i = v cc or gnd 3.3 v 5 5 pf 6.6 timing requirements, ? 40 c to +85 c over recommended operating free-air temperature range (unless otherwise noted) (see figure 3 ) parameter from to ? 40 c to +85 c unit v cc = 1.8 v 0.15 v v cc = 2.5 v 0.2 v v cc = 3.3 v 0.3 v v cc = 5 v 0.5 v min max min max min max min max f clock 80 175 175 200 mhz t w clk 6.2 2.7 2.7 2 ns pre or clr low 6.2 2.7 2.7 2 t su data 2.9 1.7 1.3 1.1 ns pre or clr inactive 1.9 1.4 1.2 1 t h 0 0.3 1.2 0.5 ns 6.7 timing requirements, ? 40 c to +125 c over recommended operating free-air temperature range (unless otherwise noted) (see figure 3 ) parameter from to ? 40 c to +125 c unit v cc = 1.8 v 0.15 v v cc = 2.5 v 0.2 v v cc = 3.3 v 0.3 v v cc = 5 v 0.5 v min max min max min max min max f clock 80 120 120 140 mhz t w clk 6.2 3.5 3.5 3.3 ns pre or clr low 6.2 3.5 3.5 3.3 t su data 2.9 2.3 1.9 1.7 ns pre or clr inactive 1.9 2 1.8 1.6 t h 0 0.3 0.5 0.5 ns
7 sn74lvc2g74 www.ti.com sces203p ? april 1999 ? revised july 2016 product folder links: sn74lvc2g74 submit documentation feedback copyright ? 1999 ? 2016, texas instruments incorporated 6.8 switching characteristics, ? 40 c to +85 c over recommended operating free-air temperature range (unless otherwise noted) (see figure 3 ) parameter from to ? 40 c to +85 c unit v cc = 1.8 v 0.15 v v cc = 2.5 v 0.2 v v cc = 3.3 v 0.3 v v cc = 5 v 0.5 v min max min max min max min max f max 80 175 175 200 mhz t pd clk q 4.8 13.4 2.2 7.1 2.2 5.9 1.4 4.1 ns q 6 14.4 3 7.7 2.6 6.2 1.6 4.4 pre or clr low q or q 4.4 12.9 2.3 7 1.7 5.9 1.6 4.1 6.9 switching characteristics, ? 40 c to +125 c over recommended operating free-air temperature range (unless otherwise noted) (see figure 3 ) parameter from to ? 40 c to +125 c unit v cc = 1.8 v 0.15 v v cc = 2.5 v 0.2 v v cc = 3.3 v 0.3 v v cc = 5 v 0.5 v min max min max min max min max f max 80 120 120 140 mhz t pd clk q 4.8 14.4 2.2 8.1 2.2 6.9 1.4 5.1 ns q 6 16 3 9.7 2.6 7.2 1.6 5.4 pre or clr low q or q 4.4 14.9 2.3 9.5 1.7 7.9 1.6 6.1 6.10 operating characteristics t a = 25 c parameter test conditions v cc = 1.8 v v cc = 2.5 v v cc = 3.3 v v cc = 5 v unit typ typ typ typ c pd power dissipation capacitance f = 10 mhz 35 35 37 40 pf 6.11 typical characteristics figure 1. propagation delay (low to high transition) vs load capacitance figure 2. propagation delay (high to low transition) vs load capacitance 2 4 6 8 10 0 50 100 150 200 250 300 c l C load capacitance C pf t C propagation delay time C ns pd v cc = 3 v, t a = 25 c one output switching 2 4 6 8 10 12 14 0 50 100 150 200 250 300 c l C load capacitance C pf v cc = 3 v, t a = 25 c one output switching t C propagation delay time C ns pd
8 sn74lvc2g74 sces203p ? april 1999 ? revised july 2016 www.ti.com product folder links: sn74lvc2g74 submit documentation feedback copyright ? 1999 ? 2016, texas instruments incorporated 7 parameter measurement information figure 3. load circuit and voltage waveforms t h t su from output under test c (see note a) l load circuit s1 v load open gnd r l data input timing input 0 v0 v 0 v t w input 0 v input output waveform 1 s1 at v (see note b) load output waveform 2 s1 at gnd (see note b) v ol v oh 0 v? 0 v outputoutput test s1 t /t plh phl open output control v m v m v m v m v m 1.8 v 0.15 v 2.5 v 0.2 v 3.3 v 0.3 v 5 v 0.5 v 1 k w 500 w 500 w 500 w v cc r l 2 v cc 2 v cc 6 v 2 v cc v load c l 30 pf30 pf 50 pf 50 pf 0.15 v0.15 v 0.3 v0.3 v v d 3 v v i v cc /2 v cc /2 1.5 v v cc /2 v m 2 ns 2 ns 2.5 ns 2.5 ns inputs r l t /t r f v cc v cc v cc v load t /t plz pzl gnd t /t phz pzh voltage waveforms enable and disable times low- and high-level enabling voltage waveforms propagation delay times inverting and noninverting outputs notes: a. c includes probe and jig capacitance. b. waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. c. all input pulses are supplied by generators having the following characteristics: prr 10 mhz, z = 50 . d. the outputs are measured one at a time, with one transition per measurement. e. t and t are the same as t . f. t and t are the same as t . g. t and t are the same as t . h. all parameters and waveforms are not applicable to all devices. l o plz phz dis pzl pzh en plh phl pd w voltage waveforms pulse duration voltage waveforms setup and hold times v i v i v i v m v m v /2 load t pzl t plz t phz t pzh v C v oh d v + v ol d v m v m v m v m v ol v oh v i v i v oh v ol v m v m v m v m t plh t phl t plh t phl
9 sn74lvc2g74 www.ti.com sces203p ? april 1999 ? revised july 2016 product folder links: sn74lvc2g74 submit documentation feedback copyright ? 1999 ? 2016, texas instruments incorporated (1) this configuration is non-stable; that is, it does not persist when pre or clr returns to its inactive (high) level. 8 detailed description 8.1 overview this device is fully specified for partial-power-down applications using i off . the i off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. 8.2 functional block diagram 8.3 feature description ? allows down voltage translation ? 5 v to 3.3 v ? 5 v or 3.3 v to 1.8v ? inputs accept voltage levels up to 5.5 v ? i off feature ? can prevent backflow current that can damage device when powered down. 8.4 device functional modes table 1 shows the functional modes of sn74lvc2g74. table 1. function table inputs outputs pre clr clk d q q l h x x h l h l x x l h l l x x h (1) h (1) h h h h l h h l l h h h l x q 0 q 0 tg c c tg cc tg c cc tg cc pre clk d clr qq c 72 6 53 1
10 sn74lvc2g74 sces203p ? april 1999 ? revised july 2016 www.ti.com product folder links: sn74lvc2g74 submit documentation feedback copyright ? 1999 ? 2016, texas instruments incorporated 9 application and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 9.1 application information a low level at the preset ( pre) or clear ( clr) input sets or resets the outputs, regardless of the levels of the other inputs. when pre and clr are inactive (high), data at the data (d) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. following the hold-time interval, data at the d input can be changed without affecting the levels at the outputs. the resistor and capacitor at the clr pin are optional. if they are not used, the clr pin should be connected directly to v cc to be inactive. 9.2 typical power button circuit figure 4. device power button circuit 9.2.1 design requirements this device uses cmos technology and has balanced output drive. care should be taken to avoid bus contention because it can drive currents that would exceed maximum limits. outputs can be combined to produce higher drive but the high drive will also create faster edges into light loads so routing and load conditions should be considered to prevent ringing. 9.2.2 detailed design procedure 1. recommended input conditions: ? for rise time and fall time specifications, see ( t/ v) in recommended operating conditions table. ? for specified high and low levels, see (v ih and v il ) in recommended operating conditions table. ? inputs are overvoltage tolerant allowing them to go as high as 5.5 v at any valid v cc 2. recommend output conditions: ? load currents should not exceed 50 ma per output and 100 ma total for the part. ? series resistors on the output may be used if the user desires to slow the output edge signal or limit the output current. d q q clr pre clk gnd vcc 3 v mcu a y nc gnd vcc 3 v sn74lvc2g74 sn74lvc1g17 3 v
11 sn74lvc2g74 www.ti.com sces203p ? april 1999 ? revised july 2016 product folder links: sn74lvc2g74 submit documentation feedback copyright ? 1999 ? 2016, texas instruments incorporated typical power button circuit (continued) 9.2.3 application curves figure 5. output current drive vs high-level output voltage figure 6. output current drive vs low-level output voltage 10 power supply recommendations the power supply can be any voltage between the minimum and maximum supply voltage rating located in the recommended operating conditions table. each v cc terminal should have a good bypass capacitor to prevent power disturbance. for devices with a single supply, a 0.1- f capacitor is recommended and if there are multiple v cc terminals then .01- f or .022- f capacitors are recommended for each power terminal. it is acceptable to parallel multiple bypass caps to reject different frequencies of noise. the 0.1- f and 1- f capacitors are commonly used in parallel. the bypass capacitor should be installed as close to the power terminal as possible for best results. v ol C v C20 0 20 40 60 80 100 C0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 t a = 25 c, v cc = 3 v, v ih = 3 v, v il = 0 v, all outputs switching i ol C ma C100 C80 C60 C40 C20 0 20 40 60 C1 C0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 t a = 25 c, v cc = 3 v, v ih = 3 v, v il = 0 v, all outputs switching v oh C v i oh C ma
12 sn74lvc2g74 sces203p ? april 1999 ? revised july 2016 www.ti.com product folder links: sn74lvc2g74 submit documentation feedback copyright ? 1999 ? 2016, texas instruments incorporated 11 layout 11.1 layout guidelines when using multiple bit logic devices, inputs should not float. in many cases, functions or parts of functions of digital logic devices are unused. some examples are when only two inputs of a triple-input and gate are used, or when only 3 of the 4-buffer gates are used. such input pins should not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. specified in figure 7 are rules that must be observed under all circumstances. all unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. the logic level that should be applied to any particular unused input depends on the function of the device. generally they will be tied to gnd or v cc , whichever makes more sense or is more convenient. it is acceptable to float outputs unless the part is a transceiver. if the transceiver has an output enable pin, it will disable the outputs section of the part when asserted. this will not disable the input section of the i/os so they also cannot float when disabled. 11.2 layout example figure 7. layout diagram v cc unused input input output input unused input output
13 sn74lvc2g74 www.ti.com sces203p ? april 1999 ? revised july 2016 product folder links: sn74lvc2g74 submit documentation feedback copyright ? 1999 ? 2016, texas instruments incorporated 12 device and documentation support 12.1 receiving notification of documentation updates to receive notification of documentation updates, navigate to the device product folder on ti.com. in the upper right corner, click on alert me to register and receive a weekly digest of any product information that has changed. for change details, review the revision history included in any revised document. 12.2 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e ? online community ti's engineer-to-engineer (e2e) community. created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. design support ti's design support quickly find helpful e2e forums along with design support tools and contact information for technical support. 12.3 trademarks nanofree, e2e are trademarks of texas instruments. all other trademarks are the property of their respective owners. 12.4 electrostatic discharge caution this integrated circuit can be damaged by esd. texas instruments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 12.5 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions. 13 mechanical, packaging, and orderable information the following pages include mechanical packaging and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser based versions of this data sheet, refer to the left hand navigation.
package option addendum www.ti.com 26-sep-2018 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples SN74LVC2G74DCT3 active sm8 dct 8 3000 pb-free (rohs) cu snbi level-1-260c-unlim -40 to 125 c74 z sn74lvc2g74dctr active sm8 dct 8 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 c74 z sn74lvc2g74dctre4 active sm8 dct 8 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 c74 z sn74lvc2g74dctre6 active sm8 dct 8 3000 pb-free (rohs) cu snbi level-1-260c-unlim -40 to 125 c74 z sn74lvc2g74dctrg4 active sm8 dct 8 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 c74 z sn74lvc2g74dcur active vssop dcu 8 3000 green (rohs & no sb/br) cu nipdau | cu sn level-1-260c-unlim -40 to 125 (74, c74q, c74r) cz sn74lvc2g74dcure4 active vssop dcu 8 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 c74r sn74lvc2g74dcurg4 active vssop dcu 8 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 c74r sn74lvc2g74dcut active vssop dcu 8 250 green (rohs & no sb/br) cu nipdau | cu sn level-1-260c-unlim -40 to 125 (c74q, c74r) sn74lvc2g74dcute4 active vssop dcu 8 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 c74r sn74lvc2g74dcutg4 active vssop dcu 8 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 c74r sn74lvc2g74yzpr active dsbga yzp 8 3000 green (rohs & no sb/br) snagcu level-1-260c-unlim -40 to 85 cpn (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) rohs: ti defines "rohs" to mean semiconductor products that are compliant with the current eu rohs requirements for all 10 rohs substances, including the requirement that rohs substance do not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, "rohs" products are suitable for use in specified lead-free processes. ti may reference these types of products as "pb-free". rohs exempt: ti defines "rohs exempt" to mean products that contain lead but are compliant with eu rohs pursuant to a specific eu rohs exemption.
package option addendum www.ti.com 26-sep-2018 addendum-page 2 green: ti defines "green" to mean the content of chlorine (cl) and bromine (br) based flame retardants meet js709b low halogen requirements of <=1000ppm threshold. antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. other qualified versions of sn74lvc2g74 : ? automotive: sn74lvc2g74-q1 ? enhanced product: sn74lvc2g74-ep note: qualified version definitions: ? automotive - q100 devices qualified for high-reliability automotive applications targeting zero defects ? enhanced product - supports defense, aerospace and medical applications
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant SN74LVC2G74DCT3 sm8 dct 8 3000 180.0 13.0 3.35 4.5 1.55 4.0 12.0 q3 sn74lvc2g74dctr sm8 dct 8 3000 180.0 13.0 3.35 4.5 1.55 4.0 12.0 q3 sn74lvc2g74dctre6 sm8 dct 8 3000 180.0 13.0 3.35 4.5 1.55 4.0 12.0 q3 sn74lvc2g74dcur vssop dcu 8 3000 180.0 8.4 2.25 3.35 1.05 4.0 8.0 q3 sn74lvc2g74dcur vssop dcu 8 3000 178.0 9.5 2.25 3.35 1.05 4.0 8.0 q3 sn74lvc2g74dcur vssop dcu 8 3000 180.0 9.0 2.05 3.3 1.0 4.0 8.0 q3 sn74lvc2g74dcurg4 vssop dcu 8 3000 180.0 8.4 2.25 3.35 1.05 4.0 8.0 q3 sn74lvc2g74dcut vssop dcu 8 250 178.0 9.5 2.25 3.35 1.05 4.0 8.0 q3 sn74lvc2g74dcutg4 vssop dcu 8 250 180.0 8.4 2.25 3.35 1.05 4.0 8.0 q3 sn74lvc2g74yzpr dsbga yzp 8 3000 178.0 9.2 1.02 2.02 0.63 4.0 8.0 q1 package materials information www.ti.com 27-sep-2018 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) SN74LVC2G74DCT3 sm8 dct 8 3000 182.0 182.0 20.0 sn74lvc2g74dctr sm8 dct 8 3000 182.0 182.0 20.0 sn74lvc2g74dctre6 sm8 dct 8 3000 182.0 182.0 20.0 sn74lvc2g74dcur vssop dcu 8 3000 202.0 201.0 28.0 sn74lvc2g74dcur vssop dcu 8 3000 202.0 201.0 28.0 sn74lvc2g74dcur vssop dcu 8 3000 182.0 182.0 20.0 sn74lvc2g74dcurg4 vssop dcu 8 3000 202.0 201.0 28.0 sn74lvc2g74dcut vssop dcu 8 250 202.0 201.0 28.0 sn74lvc2g74dcutg4 vssop dcu 8 250 202.0 201.0 28.0 sn74lvc2g74yzpr dsbga yzp 8 3000 220.0 220.0 35.0 package materials information www.ti.com 27-sep-2018 pack materials-page 2

mechanical data mpds049b ? may 1999 ? revised october 2002 post office box 655303 ? dallas, texas 75265 dct (r-pdso-g8) plastic small-outline package ????? ????? ????? ????? 0,60 0,20 0,25 0 ? 8 0,15 nom gage plane 4188781/c 09/02 4,25 5 0,30 0,15 2,90 3,75 2,70 8 4 3,15 2,75 1 0,10 0,00 1,30 max seating plane 0,10 m 0,13 0,65 pin 1 index area notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion d. falls within jedec mo-187 variation da.

www.ti.com package outline c 0.5 max 0.19 0.15 1.5 typ 0.5 typ 8x 0.25 0.21 0.5 typ b e a d 4223082/a 07/2016 dsbga - 0.5 mm max height yzp0008 die size ball grid array notes: 1. all linear dimensions are in millimeters. any dimensions in parenthesis are for reference only. dimensioning and tolerancing per asme y14.5m. 2. this drawing is subject to change without notice. ball a1 corner seating plane ball typ 0.05 c b 1 2 0.015 c a b symm symm c a d scale 8.000d: max = e: max = 1.919 mm, min = 0.918 mm, min = 1.858 mm0.857 mm
www.ti.com example board layout 8x ( 0.23) (0.5) typ (0.5) typ ( 0.23) metal 0.05 max ( 0.23) solder mask opening 0.05 min 4223082/a 07/2016 dsbga - 0.5 mm max height yzp0008 die size ball grid array notes: (continued) 3. final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. for more information, see texas instruments literature number snva009 (www.ti.com/lit/snva009). symm symm land pattern example scale:40x 1 2 a b c d non-solder mask defined (preferred) solder mask details not to scale solder mask opening solder mask defined metal under solder mask
www.ti.com example stencil design (0.5) typ (0.5) typ 8x ( 0.25) (r0.05) typ metal typ 4223082/a 07/2016 dsbga - 0.5 mm max height yzp0008 die size ball grid array notes: (continued) 4. laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. symm symm solder paste example based on 0.1 mm thick stencil scale:40x 1 2 a b c d
important notice and disclaimer ti provides technical and reliability data (including datasheets), design resources (including reference designs), application or other design advice, web tools, safety information, and other resources ? as is ? and with all faults, and disclaims all warranties, express and implied, including without limitation any implied warranties of merchantability, fitness for a particular purpose or non-infringement of third party intellectual property rights. these resources are intended for skilled developers designing with ti products. you are solely responsible for (1) selecting the appropriate ti products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. these resources are subject to change without notice. ti grants you permission to use these resources only for development of an application that uses the ti products described in the resource. other reproduction and display of these resources is prohibited. no license is granted to any other ti intellectual property right or to any third party intellectual property right. ti disclaims responsibility for, and you will fully indemnify ti and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. ti ? s products are provided subject to ti ? s terms of sale ( www.ti.com/legal/termsofsale.html ) or other applicable terms available either on ti.com or provided in conjunction with such ti products. ti ? s provision of these resources does not expand or otherwise alter ti ? s applicable warranties or warranty disclaimers for ti products. mailing address: texas instruments, post office box 655303, dallas, texas 75265 copyright ? 2018, texas instruments incorporated

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